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Design and Analysis of a Programmable Ramp Generator for Frequency Synthesizers — arXiv:2608.07680

Source: arXiv (en)
Original: https://arxiv.org/abs/2608.07680
License (as archived): CC0-1.0
Archived: 2026-10-19T09:45:24.890Z
SHA-256 of the archived text: b190b5dbc83c856876ffb42e61fe41e19a4c2625438fac9ab777db11c8560aa0
Stable URL of this page: https://metraipolis.com/documento/dc_fca1fef89900

How to cite

Design and Analysis of a Programmable Ramp Generator for Frequency Synthesizers — arXiv:2608.07680 — arXiv (en), https://arxiv.org/abs/2608.07680 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_fca1fef89900 (Metraipolis archive dc_fca1fef89900, sha256 b190b5dbc83c856876ffb42e61fe41e19a4c2625438fac9ab777db11c8560aa0)

BibTeX

@misc{dcfca1fef89900,
  title = {Design and Analysis of a Programmable Ramp Generator for Frequency Synthesizers — arXiv:2608.07680},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2608.07680},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_fca1fef89900; sha256 b190b5dbc83c856876ffb42e61fe41e19a4c2625438fac9ab777db11c8560aa0},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2608.07680. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

This paper presents a fully digital Programmable Ramp Generator (PRG) for reconfigurable frequency-ramp synthesizers used in Frequency-Modulated Continuous-Wave radar, spread-spectrum clock generation, and test and measurement applications. A novel modular architecture is proposed, integrating a phase-accumulator-based frequency sweep generator and Delta-Sigma Modulator (DSM) that drives a Multi-Modulus Divider (MMD), giving independent digital control over ramp slope, bandwidth, and duration. While prior works demonstrate chirp synthesis, the circuit-level constraints governing reliable PRG operation have not been jointly analyzed. This work identifies and analyzes three such constraints: (a) MMD octave-boundary behavior under dynamic updates, (b) divider-synchronous timing, and (c) DSM limits on step duration and achievable slope. Together, these constraints define the PRG design space, enabling a systematic algorithm that maps application-level specifications directly to hardware parameters. Following this methodology, a 16-bit PRG implemented in TSMC 65 nm CMOS is verified across 18 ramp profiles and hardware prototyping on a Xilinx Spartan-7 FPGA confirms real-time operation.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-08-11 in eess.SY).
Categorie arXiv: Systems and Control (eess.SY).
Pagina del lavoro: https://arxiv.org/abs/2608.07680 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-19T09:36:48.861Z dalla pagina https://arxiv.org/catchup/eess.SY/2026-08-11?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).