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Non-uniform Memory Partitioning For Low-Power Spiking Neural Networks — arXiv:2608.30444

Source: arXiv (en)
Original: https://arxiv.org/abs/2608.30444
License (as archived): CC0-1.0
Archived: 2026-10-17T08:19:10.355Z
SHA-256 of the archived text: 6a4e28df3a45a44895110e070b9ae99ace18e263ff1d9a74cd4708ef059eb6c2
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Non-uniform Memory Partitioning For Low-Power Spiking Neural Networks — arXiv:2608.30444 — arXiv (en), https://arxiv.org/abs/2608.30444 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_fa479ba7fa47 (Metraipolis archive dc_fa479ba7fa47, sha256 6a4e28df3a45a44895110e070b9ae99ace18e263ff1d9a74cd4708ef059eb6c2)

BibTeX

@misc{dcfa479ba7fa47,
  title = {Non-uniform Memory Partitioning For Low-Power Spiking Neural Networks — arXiv:2608.30444},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2608.30444},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_fa479ba7fa47; sha256 6a4e28df3a45a44895110e070b9ae99ace18e263ff1d9a74cd4708ef059eb6c2},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2608.30444. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Spiking Neural Networks (SNNs) naturally excel in processing temporally rich and sparse data. However, because of their time-stepped processing, memory access, specifically to synaptic weights stored in SRAM (static random-access memory), tends to dominate total power consumption. To address this issue, without incurring a large area overhead, we propose to leverage the greatly varying average firing rate of neurons in the network to efficiently allocate synaptic weights to an on-chip memory consisting of multiple non-uniformly sized memory banks. By assigning weights of frequently firing neurons to shallow, low-access cost memory and less actively accessed weights to deeper, high-density memories, the average power consumption of the synaptic weight memory is decreased without incurring a large area overhead. To benchmark our proposed architecture and find optimal configurations of memory arrangements, we perform an automatic exploration based on application requirements and hardware constraints. For memory designs synthesized in 28-nm CMOS technology, we show that our architecture can achieve a synaptic weight memory access power reduction of up to 61\% compared to a conventional design, with a 2.1$\times$ lower area overhead, as compared to a traditional uniformly partitioned memory bank that achieves a comparable reduction.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-09-01 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2608.30444 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-17T08:07:25.702Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-09-01?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).