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TALU: A Reconfigurable Tiled-ALU Grid for RISC-V — arXiv:2610.19277

Source: arXiv (en)
Original: https://arxiv.org/abs/2610.19277
License (as archived): CC0-1.0
Archived: 2026-10-15T14:08:16.103Z
SHA-256 of the archived text: 59d257af110e4b9b5935d6c83fe5bab092012a11daef6d2076c4efaa6c888a96
Stable URL of this page: https://metraipolis.com/documento/dc_f19400a18456

How to cite

TALU: A Reconfigurable Tiled-ALU Grid for RISC-V — arXiv:2610.19277 — arXiv (en), https://arxiv.org/abs/2610.19277 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_f19400a18456 (Metraipolis archive dc_f19400a18456, sha256 59d257af110e4b9b5935d6c83fe5bab092012a11daef6d2076c4efaa6c888a96)

BibTeX

@misc{dcf19400a18456,
  title = {TALU: A Reconfigurable Tiled-ALU Grid for RISC-V — arXiv:2610.19277},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2610.19277},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_f19400a18456; sha256 59d257af110e4b9b5935d6c83fe5bab092012a11daef6d2076c4efaa6c888a96},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2610.19277. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Lane-based RISC-V vector processors exploit data parallelism well but pay a recurring cost for two common patterns: reductions, which require a separate tree pass, and deep dependent expression chains, which cannot be fused and are issued as serial vector instructions. We present TALU, a 5-stage RISC-V core whose execute stage is an NxN grid of registered ALU tiles instead of a single ALU. The grid is a reconfigurable, feed-forward spatial fabric: tiles route operands only from non-backward neighbours, and added diagonal forwarding lets a reduction collapse spatially. A minimal custom extension configures the per-tile operation, routing, and per-tile constants, and streams operands through the array. On a single fabric, TALU runs ordinary scalar code, single deep-path expressions, and multi-lane vector kernels. On the benchmark suite of the RISC-V2 vector processor, TALU is 1.8-5.5x faster than RISC-V2 and 4.5-15.5x faster than Vicuna at equal lane count, with a reduction cost (dot÷add) of 1.05x versus 1.96x and 1.26x for the vector cores. A retimed implementation places and routes at 1.03 GHz in 45 nm in 0.30 mm2, half the area of RISC-V2.

Tema degli esploratori: calcolo e infrastrutture (elenco arXiv cs.AR, nuovi lavori del giorno).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2610.19277 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-15T13:50:35.378Z dalla pagina https://arxiv.org/list/cs.AR/new (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).