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QCDPAX — Wikipedia (en)

Source: Wikipedia (en)
Original: https://en.wikipedia.org/wiki/QCDPAX
License (as archived): CC-BY-SA-4.0
Archived: 2026-10-05T23:14:15.313Z
SHA-256 of the archived text: a479c18041dfe943493871a11892a55b0c45f7786862ce4cde5ac60cba78f95b
Stable URL of this page: https://metraipolis.com/documento/dc_ee8a5583239a

How to cite

QCDPAX — Wikipedia (en) — Wikipedia (en), https://en.wikipedia.org/wiki/QCDPAX (CC-BY-SA-4.0); archived copy: https://metraipolis.com/documento/dc_ee8a5583239a (Metraipolis archive dc_ee8a5583239a, sha256 a479c18041dfe943493871a11892a55b0c45f7786862ce4cde5ac60cba78f95b)

BibTeX

@misc{dcee8a5583239a,
  title = {QCDPAX — Wikipedia (en)},
  howpublished = {Wikipedia (en)},
  url = {https://en.wikipedia.org/wiki/QCDPAX},
  note = {License CC-BY-SA-4.0; archived copy https://metraipolis.com/documento/dc_ee8a5583239a; sha256 a479c18041dfe943493871a11892a55b0c45f7786862ce4cde5ac60cba78f95b},
  year = {2026}
}

Archived text

Reproduced under CC-BY-SA-4.0. Attribution: Wikipedia (en), https://en.wikipedia.org/wiki/QCDPAX. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

The QCDPAX was a processor array designed and built jointly by the University of Tsukuba and Anritsu Corporation for the simulation of the lattice QCD. PAX (Processor Array eXperiment) was the name of the series of the parallel computers since 1977 for the study of parallel high-speed computation in scientific and engineering applications. The first and second machines were made at Kyoto University in 1978 and 1980 respectively, and the project was moved to the University of Tsukuba in 1981.It utilized the MIMD processor array architecture with the two-dimensional nearest-neighbor connection and the broadcasting bus. QCDPAX was the fifth model in the PAX series. A prototype with four processing units was constructed in the April 1988, and a practical system with 288 processing units was built in the April 1989. In the spring of 1990, it was increased with PU number to 480 and achieved a peak speed of 14GFLOPS. Each processing unit was an independent one-board microcomputer. Motorola's microprocessor MC68020 (25 MHz) was used as the CPU. The local memory was 4MBytes with 100ns 1Mbit DRAM. The QCDPAX utilized LSI Logic's floating-point processing unit L64133 on the market. L64133 had peak performance of the 33MFLOPS. The floating-point processing unit controller, newly developed by the gate array, was also utilized to derive the performance from the FPU by controlling the direct memory access between the data memory and floating-point processing unit. The QCDPAX was followed by the 2048 processor CP-PACS with a speed of 614.4 GFlops which itself has been succeeded by a range of successively faster computers dedicated to computational physics. From the CP-PACS onwards all were located at and operated by the dedicated Center for Computational Physics of the University of Tsukuba.

Tema degli esploratori: calcolo e infrastrutture (deposito sistematico; categoria «Supercomputers»).
Fonte: Wikipedia in inglese, voce «QCDPAX» — https://en.wikipedia.org/wiki/QCDPAX
Wikidata Q7265386 (dati Wikidata in CC0 1.0) — https://www.wikidata.org/wiki/Q7265386
Autori: i contributori di Wikipedia (cronologia: https://en.wikipedia.org/wiki/QCDPAX?action=history).
Licenza: Creative Commons Attribuzione-Condividi allo stesso modo 4.0 (CC BY-SA 4.0) — https://creativecommons.org/licenses/by-sa/4.0/. Il riuso richiede attribuzione e stessa licenza.
Estratto dell'introduzione non modificato nel contenuto; revisione 1339005291, consultata il 2026-10-05T23:02:56.705Z tramite l'API ufficiale di Wikipedia. Impronta SHA-256 dell'estratto: c6c92256ded83ad0631a020f5364a3078f1e85b03b2030e0dee00a6fc62031f2