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AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting — arXiv:2610.33088

Source: arXiv (en)
Original: https://arxiv.org/abs/2610.33088
License (as archived): CC0-1.0
Archived: 2026-10-27T07:59:35.385Z
SHA-256 of the archived text: b650cb7d0c8830810cbf417d37c2179c93f8266787c6a5dba26caf40deba8fde
Stable URL of this page: https://metraipolis.com/documento/dc_ebad45bf7fe5

How to cite

AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting — arXiv:2610.33088 — arXiv (en), https://arxiv.org/abs/2610.33088 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_ebad45bf7fe5 (Metraipolis archive dc_ebad45bf7fe5, sha256 b650cb7d0c8830810cbf417d37c2179c93f8266787c6a5dba26caf40deba8fde)

BibTeX

@misc{dcebad45bf7fe5,
  title = {AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting — arXiv:2610.33088},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2610.33088},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_ebad45bf7fe5; sha256 b650cb7d0c8830810cbf417d37c2179c93f8266787c6a5dba26caf40deba8fde},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2610.33088. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Analog circuit design still relies heavily on expert knowledge, and porting proven designs to new process nodes is a recurring bottleneck. As a lower supply reduces available voltage headroom, a working topology may require redesign or fail to meet specifications. While large language models (LLMs) have begun to generate and optimize analog circuits, existing benchmarks focus on one process node and assume feasible specifications. To bridge this gap, we introduce AnalogPortBench, a benchmark of 54 tasks for porting ten circuits, from current mirrors to telescopic amplifiers, from a 0.18 $\mu$m process to the open-source SKY130 PDK. Tasks range from a direct port through a reduced supply and harder specifications to infeasible ones, and every feasible task has a reference design verified at five process corners. Evaluating six frontier LLMs at two reasoning levels, with and without simulation feedback, we find that models port simple circuits but rarely re-design headroom-sensitive amplifiers, seldom recognize infeasible specifications, and gain more from simulation feedback than from more samples or reasoning. Code and data are available at this https URL .

Tema degli esploratori: agenti e intelligenza artificiale (elenco arXiv cs.AI, nuovi lavori del giorno).
Categorie arXiv: Hardware Architecture (cs.AR) ; Artificial Intelligence (cs.AI).
Pagina del lavoro: https://arxiv.org/abs/2610.33088 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-27T07:55:30.808Z dalla pagina https://arxiv.org/list/cs.AI/new (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).