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FAPO: Fanout-Aware Post-Mapping Optimization for LUT-Based FPGAs — arXiv:2610.06937

Source: arXiv (en)
Original: https://arxiv.org/abs/2610.06937
License (as archived): CC0-1.0
Archived: 2026-10-07T11:25:35.354Z
SHA-256 of the archived text: fd31309d1a850a6981123816297b62de029e5f079fe31b4c8f6af15adf895ac3
Stable URL of this page: https://metraipolis.com/documento/dc_ea578de751df

How to cite

FAPO: Fanout-Aware Post-Mapping Optimization for LUT-Based FPGAs — arXiv:2610.06937 — arXiv (en), https://arxiv.org/abs/2610.06937 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_ea578de751df (Metraipolis archive dc_ea578de751df, sha256 fd31309d1a850a6981123816297b62de029e5f079fe31b4c8f6af15adf895ac3)

BibTeX

@misc{dcea578de751df,
  title = {FAPO: Fanout-Aware Post-Mapping Optimization for LUT-Based FPGAs — arXiv:2610.06937},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2610.06937},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_ea578de751df; sha256 fd31309d1a850a6981123816297b62de029e5f079fe31b4c8f6af15adf895ac3},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2610.06937. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Reducing logic depth during FPGA technology mapping does not necessarily eliminate fanout bottlenecks in the resulting LUT this http URL heavily loaded LUTs can alleviate these bottlenecks, but the added copies consume area and may increase upstream loading. We propose FAPO, a mapper-independent post-mapping optimizer that jointly refines sink assignments and LUT cuts under a final-area this http URL , cut switching, and recovery are evaluated by the resulting live LUT this http URL derive a necessary all-critical-path condition for delay reduction and obtain minimum-copy proposals by minimum cut within a restricted same-cut this http URL proposals complement greedy refinement, with mappings selected by full-network area and this http URL on EPFL benchmarks with three initial mappers achieve geometric-mean reductions of up to 14.48% in fanout-aware area--timing product (ATP) with a 5% final-area this http URL evaluation shows a 7.04% reduction in routed critical-path delay relative to ABC if.

Tema degli esploratori: calcolo e infrastrutture (elenco arXiv cs.AR, nuovi lavori del giorno).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2610.06937 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-07T11:16:09.452Z dalla pagina https://arxiv.org/list/cs.AR/new (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).