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Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs — arXiv:2609.18846

Source: arXiv (en)
Original: https://arxiv.org/abs/2609.18846
License (as archived): CC0-1.0
Archived: 2026-10-15T13:58:01.881Z
SHA-256 of the archived text: 2ccf7f448a0d828810539fd5f157bae283641b1b3a2cbe24d48ff89eec33aa7b
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How to cite

Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs — arXiv:2609.18846 — arXiv (en), https://arxiv.org/abs/2609.18846 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_e7df2fcecd31 (Metraipolis archive dc_e7df2fcecd31, sha256 2ccf7f448a0d828810539fd5f157bae283641b1b3a2cbe24d48ff89eec33aa7b)

BibTeX

@misc{dce7df2fcecd31,
  title = {Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs — arXiv:2609.18846},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2609.18846},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_e7df2fcecd31; sha256 2ccf7f448a0d828810539fd5f157bae283641b1b3a2cbe24d48ff89eec33aa7b},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2609.18846. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Zero-Knowledge Proofs (ZKPs) are critical for privacy-preserving and verifiable computation, but their cryptographic primitives impose high computational overheads. One such primitive is point addition (PADD) on elliptic curves. Several prior works have implemented PADDs in hardware, but only for a few specific elliptic curves and design points, leaving a large design space unexplored, and lacking systematic guidance on hardware design trade-offs. To address this gap, we present Locus, a framework dedicated to optimizing and exploring point addition hardware. Given the parameters of any elliptic curve in a supported equation form, Locus automatically generates ASIC and FPGA implementations of PADD, enabling systematic exploration of the PADD design space. Using Locus, we conduct the first comprehensive hardware-focused study of PADD designs, exploring trade-offs over 1,000 design points. On a 12nm technology node, our framework produces PADD designs that yield a $2.71\times$ geomean speedup and $3.11\times$ geomean area reduction compared to prior ASICs, $34.67\times$ geomean speedup over CPU, and $3.15\times$ geomean speedup on end-to-end proof generation when integrated into a prior ZKP accelerator at iso-area. Locus is available at this https URL .

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-09-17 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR) ; Cryptography and Security (cs.CR).
Pagina del lavoro: https://arxiv.org/abs/2609.18846 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-15T13:49:21.822Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-09-17?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).