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A Framework for Accelerating Transformer Inference on RISC-V for Edge AI — arXiv:2610.08688

Source: arXiv (en)
Original: https://arxiv.org/abs/2610.08688
License (as archived): CC0-1.0
Archived: 2026-10-07T11:25:42.812Z
SHA-256 of the archived text: bdc4f5290e824f5f47a441ac90bb9400868f6d3f0bf9939cea46d7f689822ef7
Stable URL of this page: https://metraipolis.com/documento/dc_e3ee112e8f2a

How to cite

A Framework for Accelerating Transformer Inference on RISC-V for Edge AI — arXiv:2610.08688 — arXiv (en), https://arxiv.org/abs/2610.08688 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_e3ee112e8f2a (Metraipolis archive dc_e3ee112e8f2a, sha256 bdc4f5290e824f5f47a441ac90bb9400868f6d3f0bf9939cea46d7f689822ef7)

BibTeX

@misc{dce3ee112e8f2a,
  title = {A Framework for Accelerating Transformer Inference on RISC-V for Edge AI — arXiv:2610.08688},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2610.08688},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_e3ee112e8f2a; sha256 bdc4f5290e824f5f47a441ac90bb9400868f6d3f0bf9939cea46d7f689822ef7},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2610.08688. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

This work presents a framework for accelerating transformer-based language models (LMs) on resource-constrained IoT devices. The framework targets compact LMs: BERT-Tiny (B-Ty), MobileBERT (M-Bt), MiniLM (M-Lm), Electra (E-Lt) and DeBERTa (D-Bt) -- selected for their architectural diversity and use in edge inference scenarios. The proposed flow derives lightweight instruction set extensions tailored to the non-obvious computational patterns of these models. In addition, a custom instruction is introduced to accelerate the address generation stage of batch matrix multiplication, achieving a performance improvement of 15.39--21.74% with modest ASIC overheads of 6.79% in area and 2.33% in power. To further enhance performance without incurring additional processor core hardware cost, an optional compiler-directed loop unrolling strategy is employed, trading increased code size for overall reduced execution time. Evaluation on the Synopsys trv32p3f RISC-V core demonstrates inference speedups of up to 2.19x, and FPGA implementation on the AMD Zynq UltraScale+ ZCU102 shows a 32.94% area overhead at 75 MHz, whereas the ASIC implementation using the TSMC 28 nm library incurs a 21.08% area overhead while operating at 250 MHz.

Tema degli esploratori: calcolo e infrastrutture (elenco arXiv cs.AR, nuovi lavori del giorno).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2610.08688 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-07T11:16:09.466Z dalla pagina https://arxiv.org/list/cs.AR/new (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).