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You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors — arXiv:2608.11116

Source: arXiv (en)
Original: https://arxiv.org/abs/2608.11116
License (as archived): CC0-1.0
Archived: 2026-10-19T06:14:40.772Z
SHA-256 of the archived text: b47b9df6f16138fc676f9a456208641eacaa0cfb8fe9905010194c8faa5e0055
Stable URL of this page: https://metraipolis.com/documento/dc_df4e4bd641d2

How to cite

You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors — arXiv:2608.11116 — arXiv (en), https://arxiv.org/abs/2608.11116 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_df4e4bd641d2 (Metraipolis archive dc_df4e4bd641d2, sha256 b47b9df6f16138fc676f9a456208641eacaa0cfb8fe9905010194c8faa5e0055)

BibTeX

@misc{dcdf4e4bd641d2,
  title = {You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors — arXiv:2608.11116},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2608.11116},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_df4e4bd641d2; sha256 b47b9df6f16138fc676f9a456208641eacaa0cfb8fe9905010194c8faa5e0055},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2608.11116. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Analog Computing-in-Memory (ACiM) accelerates deep neural networks by keeping weights inside memory arrays and executing dot products in the analog domain. However, modern ACiM accelerators are often limited by the "ADC wall": analog-to-digital converters consume a large fraction of energy and area, while bit-sliced execution repeatedly invokes these converters. Existing designs reduce this cost with low-resolution readout or time multiplexing, but they either lose output fidelity or introduce serialization overhead. Charge-CIM addresses this bottleneck by using switched-capacitor charge redistribution as a unified computing and conversion substrate. The same capacitor fabric performs input conversion, analog MAC, weighted shift-and-add, and readout quantization, reducing both standalone converter overhead and intermediate ADC invocations. A differential readout path further combines paired partial sums during ADC quantization, providing a highly compact and energy-efficient solution for array integration. With dataflow architecture support, we evaluated Charge-CIM on a suite of DNN benchmarks, from CNNs to Transformer models, and experimental results show that Charge-CIM reduces ADC energy by 91.7% under our evaluation setup and improves energy efficiency by 2.7x and throughput by 2.0x compared to the state-of-the-art charge-domain CIM accelerator.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-08-12 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2608.11116 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-19T06:09:22.681Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-08-12?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).