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HippocamFLEX: FPGA Prototyping of Hippocampus-Inspired Architecture for Context-Aware Sequence Prediction — arXiv:2610.40932

Source: arXiv (en)
Original: https://arxiv.org/abs/2610.40932
License (as archived): CC0-1.0
Archived: 2026-11-03T08:07:21.230Z
SHA-256 of the archived text: 2829c58385b3402e9e95aa13b3b67e4482ba34bfa806b5eb5f048cf4c354d58c
Stable URL of this page: https://metraipolis.com/documento/dc_cded1ab2a537

How to cite

HippocamFLEX: FPGA Prototyping of Hippocampus-Inspired Architecture for Context-Aware Sequence Prediction — arXiv:2610.40932 — arXiv (en), https://arxiv.org/abs/2610.40932 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_cded1ab2a537 (Metraipolis archive dc_cded1ab2a537, sha256 2829c58385b3402e9e95aa13b3b67e4482ba34bfa806b5eb5f048cf4c354d58c)

BibTeX

@misc{dccded1ab2a537,
  title = {HippocamFLEX: FPGA Prototyping of Hippocampus-Inspired Architecture for Context-Aware Sequence Prediction — arXiv:2610.40932},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2610.40932},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_cded1ab2a537; sha256 2829c58385b3402e9e95aa13b3b67e4482ba34bfa806b5eb5f048cf4c354d58c},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2610.40932. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Unlike conventional architectures that treat memory as static pattern storage, the hippocampus organizes experience as ordered sequences and retrieves them through temporally compressed replay spanning prior, current, and anticipated states. This capacity of context-appropriate sequence prediction remains absent from conventional deep learning accelerators and existing neuromorphic fabrics. We present HippocamFLEX, a fully synthesizable digital implementation of these hippocampal computational principles, realized with SystemVerilog RTL on the AMD Zynq UltraScale+,XCZU9EG. The design maps the hippocampal trisynaptic pathway onto three pipeline stages: a Dentate Gyrus / Entorhinal Cortex (DG/EC) stage for hypervector proximity matching, a CA3 stage for context-gated recurrent sequence prediction with multi-phase temporal tagging, and a CA1 stage that integrates past, present, and predicted future events into a theta-sequence inspired output. While much brain-inspired hardware relies on analog mixed-signal design for energy efficiency, this work targets FPGA prototyping as a deliberate architectural choice: FPGAs offer rapid design-space exploration without tape-out cost, bit-exact determinism that simplifies verification. The design supports 64 events across 16 contexts and is verified on physical silicon across context-isolation, temporal-ordering, and mid-sequence sliding-window test cases and is inherently scalable to larger event and context sets.

Tema degli esploratori: calcolo e infrastrutture (elenco arXiv cs.AR, nuovi lavori del giorno).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2610.40932 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-11-03T08:00:23.551Z dalla pagina https://arxiv.org/list/cs.AR/new (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).