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VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration — arXiv:2608.23404

Source: arXiv (en)
Original: https://arxiv.org/abs/2608.23404
License (as archived): CC0-1.0
Archived: 2026-10-18T07:56:09.783Z
SHA-256 of the archived text: 005e7e18e3b0fc1df0b66b0fa2b1fe362619cf1a36afbcd6fe6adf2d0d2a35f6
Stable URL of this page: https://metraipolis.com/documento/dc_c155bf55ff8b

How to cite

VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration — arXiv:2608.23404 — arXiv (en), https://arxiv.org/abs/2608.23404 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_c155bf55ff8b (Metraipolis archive dc_c155bf55ff8b, sha256 005e7e18e3b0fc1df0b66b0fa2b1fe362619cf1a36afbcd6fe6adf2d0d2a35f6)

BibTeX

@misc{dcc155bf55ff8b,
  title = {VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration — arXiv:2608.23404},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2608.23404},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_c155bf55ff8b; sha256 005e7e18e3b0fc1df0b66b0fa2b1fe362619cf1a36afbcd6fe6adf2d0d2a35f6},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2608.23404. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Processing-in-Memory (PIM) promises to reduce data movement overhead by executing computation in or near memory, but its realized application speedup remains highly design-dependent. Non-offloadable host execution, host-PIM transfers, limited PIM capacity, and device programming latency can limit end-to-end speedup, making fast early-stage design-space exploration (DSE) essential. However, existing PIM evaluation methods remain limited: circuit- and device-level tools cannot capture these end-to-end PIM performance factors, while cycle-accurate simulation is too slow for iterative DSE. To address this gap, we present VIPER, a unified, lightweight, and architecture-aware performance evaluation framework for PIM DSE. VIPER profiles host execution once and combines the measured host behavior with a PIM-aware analytical engine that sweeps PIM-side parameters across candidate designs. It supports both Processing Near Memory (PNM) and Processing Using Memory (PUM) under task-offloading and data-triggered execution by capturing host-PIM transfer, array access, in-memory computation, device programming latency, and capacity-induced partitioning, providing rapid architecture-aware performance estimates for iterative DSE without repeated cycle-accurate simulation. We validate VIPER against a commercial UPMEM system and more than 400 cycle-accurate gem5 configurations. VIPER predicts the UPMEM offloading decision and break-even region a priori, and, with a refined transfer model, captures the measured peak-and-rolloff behavior with 12\% mean speedup error across the DPU sweep (6\% up to the 256-DPU peak). Against gem5, VIPER achieves less than 10\% error while reducing evaluation time from hours to under one minute. Case studies of UPMEM, ReRAM/FeFET crossbars, and IMCRYPTO show that architecture-aware DSE reveals key performance trade-offs that device-level evaluation misses.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-08-25 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2608.23404 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-18T07:48:03.870Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-08-25?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).