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Superscalar Loop Processors — arXiv:2611.01904

Source: arXiv (en)
Original: https://arxiv.org/abs/2611.01904
License (as archived): CC0-1.0
Archived: 2026-11-03T18:26:50.310Z
SHA-256 of the archived text: 075036a66ef5e02fde1e18fea041a3c5442d208e17dbeecb7f54eefa224438f0
Stable URL of this page: https://metraipolis.com/documento/dc_ae1148deffbf

How to cite

Superscalar Loop Processors — arXiv:2611.01904 — arXiv (en), https://arxiv.org/abs/2611.01904 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_ae1148deffbf (Metraipolis archive dc_ae1148deffbf, sha256 075036a66ef5e02fde1e18fea041a3c5442d208e17dbeecb7f54eefa224438f0)

BibTeX

@misc{dcae1148deffbf,
  title = {Superscalar Loop Processors — arXiv:2611.01904},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2611.01904},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_ae1148deffbf; sha256 075036a66ef5e02fde1e18fea041a3c5442d208e17dbeecb7f54eefa224438f0},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2611.01904. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

To sustain the computational demands of modern ML and HPC workloads, programmable accelerators integrate large arrays of processing elements (PEs), typically built around single-issue in-order cores to maximize integration density and energy efficiency. As a result, each PE's instruction throughput is upper-bounded at one instruction per cycle (IPC), often suffering from significant underutilization of its functional units (FUs). Conventional superscalar processors can improve FU utilization by increasing IPC, but they typically incur substantial area and energy overheads. This work proposes the Superscalar Loop Processor (SLP) architecture, a lightweight approach to superscalar execution that targets regular, compute-intensive loop kernels. We present the SLP execution model, which exploits the static structure of these workloads to enable efficient multiple-issue execution without the complexity of dynamic out-of-order scheduling. We demonstrate the SLP architecture through an open-source prototype implementation, Schnizo, developed as an enhancement of a tiny RV32I core with floating-point support. Across several ML and HPC microkernels, Schnizo achieves substantially higher IPC and FPU utilization than the scalar baseline while retaining the efficiency of lightweight in-order designs. These results demonstrate that SLPs can provide an efficient architectural solution for programmable accelerators targeting regular, compute-intensive workloads.

Tema degli esploratori: calcolo e infrastrutture (elenco arXiv cs.DC, nuovi lavori del giorno).
Categorie arXiv: Hardware Architecture (cs.AR) ; Distributed, Parallel, and Cluster Computing (cs.DC).
Pagina del lavoro: https://arxiv.org/abs/2611.01904 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-11-03T18:10:22.856Z dalla pagina https://arxiv.org/list/cs.DC/new (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).