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Low-level optimizations in high-level HDLs: Is there a benefit? — arXiv:2609.37021

Source: arXiv (en)
Original: https://arxiv.org/abs/2609.37021
License (as archived): CC0-1.0
Archived: 2026-10-07T16:59:17.746Z
SHA-256 of the archived text: 32e2dd4f5c4b043c932afeb65963b2b5f61d151389fe7a0e374551e9d710030e
Stable URL of this page: https://metraipolis.com/documento/dc_84512e490bf4

How to cite

Low-level optimizations in high-level HDLs: Is there a benefit? — arXiv:2609.37021 — arXiv (en), https://arxiv.org/abs/2609.37021 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_84512e490bf4 (Metraipolis archive dc_84512e490bf4, sha256 32e2dd4f5c4b043c932afeb65963b2b5f61d151389fe7a0e374551e9d710030e)

BibTeX

@misc{dc84512e490bf4,
  title = {Low-level optimizations in high-level HDLs: Is there a benefit? — arXiv:2609.37021},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2609.37021},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_84512e490bf4; sha256 32e2dd4f5c4b043c932afeb65963b2b5f61d151389fe7a0e374551e9d710030e},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2609.37021. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

This paper explores the applicability of functional programming to the design of Application-specific Integrated Circuits (ASICs). We investigate the impact of designing ASICs using high-level, abstract Hardware Description Language (HDL) features versus employing low-level optimizations on the area of the synthesized circuits. The aim is to determine whether using low-level optimizations is beneficial and, if so, whether it is worth the added implementation effort. To carry out the investigation, we implement an unsigned bit-serial multiply-accumulate (MAC) unit in 16 different configurations using the functional HDL Clash. We make use of both low-level bit-manipulation techniques as well as Clash's high-level constructs for circuit design. The experimental evaluation shows that some high-level constructs of Clash have negligible influence on the resulting circuit size, suggesting that using the full power of functional programming is a viable approach to hardware design. To evaluate the impact of the used HDL itself, we also implemented versions of the MAC in Verilog. The experiments clearly show that there seems to be an inherent overhead in using Clash compared to Verilog code written by a seasoned engineer.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-09-30 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2609.37021 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-07T16:31:49.771Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-09-30?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).