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A Low-Latency ASIC Architecture for Real-Time Line Segment Detection — arXiv:2608.06439

Source: arXiv (en)
Original: https://arxiv.org/abs/2608.06439
License (as archived): CC0-1.0
Archived: 2026-10-19T09:48:20.668Z
SHA-256 of the archived text: 12113dded6f68ea70f9424d23746465ffecf5f3886d5851839bc2a611be69b20
Stable URL of this page: https://metraipolis.com/documento/dc_7eaba477fcfb

How to cite

A Low-Latency ASIC Architecture for Real-Time Line Segment Detection — arXiv:2608.06439 — arXiv (en), https://arxiv.org/abs/2608.06439 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_7eaba477fcfb (Metraipolis archive dc_7eaba477fcfb, sha256 12113dded6f68ea70f9424d23746465ffecf5f3886d5851839bc2a611be69b20)

BibTeX

@misc{dc7eaba477fcfb,
  title = {A Low-Latency ASIC Architecture for Real-Time Line Segment Detection — arXiv:2608.06439},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2608.06439},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_7eaba477fcfb; sha256 12113dded6f68ea70f9424d23746465ffecf5f3886d5851839bc2a611be69b20},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2608.06439. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Line segment detection is a critical preprocessing step in embedded vision applications such as autonomous navigation, visual SLAM, and industrial inspection. Deep learning methods achieve high accuracy but require substantial resources, limiting their deployment on resource-constrained platforms. Classical algorithms are efficient but exhibit content-dependent latency. This paper presents a low-latency ASIC architecture for real-time line segment detection. The proposed design is based on the step-length algorithm and incorporates five ASIC-specific features: register-based line buffering with data reuse, multiplierless MCM-based filtering, 8-class angle quantization, a CAM-like associative memory for single-cycle matching, and an optimized duplicate removal mechanism. The architecture is fully pipelined and processes one pixel per clock cycle with deterministic latency. Synthesized in a 45nm CMOS process, the design achieves 325 FPS at VGA resolution and 48 FPS at Full HD, with 25.54 mW power consumption and 0.412 mm\textsuperscript{2} area. At 125 MHz, the throughput increases to 406 FPS at VGA resolution with 31.48 mW power consumption. Compared with a 90nm ASIC implementation based on the Line Hough Transform, the proposed design reduces power consumption by 49\% and delivers over 1.6 times higher frame rate. The architecture is well suited for edge-computing applications requiring real-time performance, low power, and minimal area.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-08-10 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2608.06439 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-19T09:47:34.747Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-08-10?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).