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Adapting DNNs to Embrace Voltage Scaling Induced Errors via Accumulation-Aware Quantization — arXiv:2610.33824

Source: arXiv (en)
Original: https://arxiv.org/abs/2610.33824
License (as archived): CC0-1.0
Archived: 2026-10-27T08:00:30.814Z
SHA-256 of the archived text: b8c0da0c8024a140c7451fea8e34fcb5b03b8308b54bafa5a969ec9896910456
Stable URL of this page: https://metraipolis.com/documento/dc_7616612675fb

How to cite

Adapting DNNs to Embrace Voltage Scaling Induced Errors via Accumulation-Aware Quantization — arXiv:2610.33824 — arXiv (en), https://arxiv.org/abs/2610.33824 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_7616612675fb (Metraipolis archive dc_7616612675fb, sha256 b8c0da0c8024a140c7451fea8e34fcb5b03b8308b54bafa5a969ec9896910456)

BibTeX

@misc{dc7616612675fb,
  title = {Adapting DNNs to Embrace Voltage Scaling Induced Errors via Accumulation-Aware Quantization — arXiv:2610.33824},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2610.33824},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_7616612675fb; sha256 b8c0da0c8024a140c7451fea8e34fcb5b03b8308b54bafa5a969ec9896910456},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2610.33824. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

The pervasive deployment of Deep Neural Networks (DNNs) across the computing spectrum has brought growing attention to energy efficiency, alongside raw performance. While voltage scaling is a potent knob for power reduction, its application in next-generation nodes is hampered by severe throughput degradation and susceptibility to process variation. This work aims to address these energy-reliability trade-offs by introducing a hardware-software co-design methodology, based on the observation that timing-robust bit ranges within the accumulator of a systolic array vary significantly across different voltage-frequency operating points. At the software level, we propose an Accumulation-Aware Training approach that incorporates this information as a first-order optimization constraint during training. By integrating mixed-precision quantization with unstructured pruning, we effectively constrain the model's weight distribution to avoid activating the hardware's sensitized high-rank carry chains. At the architectural level, we complement this with selective MSB-masking and fine-grained clock-gating to minimize unnecessary dynamic switching activity. Furthermore, we employ a layer-wise Dynamic Frequency Scaling strategy to further adapt to the accumulator's reduced dynamic range, based on the numerical sensitivity of each layer. We experimentally evaluate the proposed solution on a deep scaled 2nm technology node and demonstrate that, when operating at a low-voltage frontier, our co-optimized post-layout architecture delivers substantial energy and energy-delay product gains of 39% and 23% respectively, relative to the nominal voltage implementation, while maintaining accuracy degradation within 1%.

Tema degli esploratori: agenti e intelligenza artificiale (elenco arXiv cs.AI, nuovi lavori del giorno).
Categorie arXiv: Hardware Architecture (cs.AR) ; Artificial Intelligence (cs.AI).
Pagina del lavoro: https://arxiv.org/abs/2610.33824 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-27T07:55:30.858Z dalla pagina https://arxiv.org/list/cs.AI/new (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).