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A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation — arXiv:2609.16600

Source: arXiv (en)
Original: https://arxiv.org/abs/2609.16600
License (as archived): CC0-1.0
Archived: 2026-10-15T19:29:46.238Z
SHA-256 of the archived text: 40b57d58e341397b922b77d0f128f9260b36791722c4cce708f6b2e65625e2ca
Stable URL of this page: https://metraipolis.com/documento/dc_6ddec95f8a2e

How to cite

A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation — arXiv:2609.16600 — arXiv (en), https://arxiv.org/abs/2609.16600 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_6ddec95f8a2e (Metraipolis archive dc_6ddec95f8a2e, sha256 40b57d58e341397b922b77d0f128f9260b36791722c4cce708f6b2e65625e2ca)

BibTeX

@misc{dc6ddec95f8a2e,
  title = {A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation — arXiv:2609.16600},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2609.16600},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_6ddec95f8a2e; sha256 40b57d58e341397b922b77d0f128f9260b36791722c4cce708f6b2e65625e2ca},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2609.16600. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Edge devices demand for highly efficient yet flexible processing capability to handle dynamic real-time workloads. Coarse grain reconfigurable architecture (CGRA) emerges as a suitable accelerator candidate in edge devices, because they are as flexible as general purpose processors and offer high efficiency close to that of domain specific accelerators. However, a typical CGRA requires two cycles for a multiply-and-accumulate (MAC) operation, and workloads such as neural network inference and signal processing involve many MAC operations, resulting in long CGRA processing time. This work proposes a CGRA that has configurable MAC units in the processing elements (PEs) that can perform an addition (ADD) or multiplication (MUL) or a MAC by using the same multiplier and adder, in a single cycle. The readout precision of MAC result can be adjusted by a truncation block. The proposed CGRA is implemented with 40nm CMOS technology. It attains an energy efficiency of 420.6GOPS/W operating at supply of 0.6V and frequency of 21MHz, which is 1.4 times higher than the state-of-the-art.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-09-16 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2609.16600 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-15T18:35:20.267Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-09-16?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).