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SYNTLOG: FSM Benchmarks Evaluation for FPGA — arXiv:2608.23288

Source: arXiv (en)
Original: https://arxiv.org/abs/2608.23288
License (as archived): CC0-1.0
Archived: 2026-10-18T07:56:09.775Z
SHA-256 of the archived text: d975a45c3306b60fe935607047149f302fff1cd0156e12f10cb27e74c569eeaf
Stable URL of this page: https://metraipolis.com/documento/dc_628f36dfbb2a

How to cite

SYNTLOG: FSM Benchmarks Evaluation for FPGA — arXiv:2608.23288 — arXiv (en), https://arxiv.org/abs/2608.23288 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_628f36dfbb2a (Metraipolis archive dc_628f36dfbb2a, sha256 d975a45c3306b60fe935607047149f302fff1cd0156e12f10cb27e74c569eeaf)

BibTeX

@misc{dc628f36dfbb2a,
  title = {SYNTLOG: FSM Benchmarks Evaluation for FPGA — arXiv:2608.23288},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2608.23288},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_628f36dfbb2a; sha256 d975a45c3306b60fe935607047149f302fff1cd0156e12f10cb27e74c569eeaf},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2608.23288. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

We introduce a curated benchmark collection of \num{101} FSM descriptions organized into five size classes (\emph{small}, \emph{medium}, \emph{large}, \emph{huge}, \emph{super-huge}), spanning tens to thousands of states and up to hundreds of inputs and outputs. Using these benchmarks we compare an architecture-independent synthesis tool SYNTLOG against Xilinx Vivado at the synthesis (technology-mapping) level, under six optimization strategies. We compare three post-synthesis parameters: number of LUTs, number of logic levels, and runtime. SYNTLOG in area-driven mode uses substantially fewer LUTs than Vivado's area baseline at every size ($-45\%$ to $-66\%$), and its delay-driven mode is simultaneously shallower in logic depth than Vivado's default synthesis mode. SYNTLOG synthesis includes embedded functional validation. Runtime of SYNTLOG is faster by one to two orders of magnitude than Vivado synthesis. The proposed tool synthesizes and validates every \emph{huge} and \emph{super-huge} circuit in minutes, whereas Vivado fails to terminate on these designs after hours.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-08-25 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2608.23288 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-18T07:48:03.869Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-08-25?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).