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A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System — arXiv:2609.13563

Source: arXiv (en)
Original: https://arxiv.org/abs/2609.13563
License (as archived): CC0-1.0
Archived: 2026-10-15T23:46:01.090Z
SHA-256 of the archived text: 9386f28467e0312ded16b6984c7128e547e42e95349bd0937ae1ea80b913ae09
Stable URL of this page: https://metraipolis.com/documento/dc_55166687f2bb

How to cite

A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System — arXiv:2609.13563 — arXiv (en), https://arxiv.org/abs/2609.13563 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_55166687f2bb (Metraipolis archive dc_55166687f2bb, sha256 9386f28467e0312ded16b6984c7128e547e42e95349bd0937ae1ea80b913ae09)

BibTeX

@misc{dc55166687f2bb,
  title = {A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System — arXiv:2609.13563},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2609.13563},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_55166687f2bb; sha256 9386f28467e0312ded16b6984c7128e547e42e95349bd0937ae1ea80b913ae09},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2609.13563. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

The BrainScaleS-2 (BSS-2) neuromorphic architecture combines analog emulation of spiking neural network (SNN) primitives with tightly coupled ADCs and digital processing units. These analog SNN primitives are fixed hardware resources that cannot be multiplexed, limiting the emulated network size to the number of physical hardware copies. To overcome the challenges of scaling analog designs, chiplet-based designs offer a promising approach with cost and flexibility advantages over monolithic scaling. Implementing a chiplet-based BSS-2 architecture requires an interconnection network that handles two distinct classes of traffic: error-tolerant traffic such as spikes and error-intolerant traffic like configuration data or data exchanged by the processing units. This work presents the design of a routing chiplet for the BSS-2 architecture that enables interconnection of multiple BSS-2 units in a 2D mesh topology. Both traffic classes are multiplexed over a single wide parallel die-to-die link. Exploiting the fault tolerance of SNNs, spikes are transmitted unsecured and synchronously, with the arrival time on the receiving side directly determining the pre-synaptic time of the spike. Conversely, error-intolerant data transmission is secured by a point-to-point Automatic Repeat Request protocol and uses credit-based flow control. These design choices are validated in simulation, where the proposed design can sustain $95\,\%$ link bandwidth utilization for the use case of surrogate gradient training across a wide range of spike-to-secured traffic ratios under a $1 \times 10^{-10}$ bit error rate with little impact on spike timing jitter.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-09-15 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2609.13563 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-15T23:13:34.582Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-09-15?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).