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Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM — arXiv:2609.36111

Source

arXiv (en)

Original

https://arxiv.org/abs/2609.36111

License (as archived)

CC0-1.0

Archived

2026-10-07T16:59:16.191Z

SHA-256 of the archived text

54cf85ce3e4ff5117b1596431d88f82f26e278bf40a9f2c26e35f9eba28157a3

Stable URL of this page

https://metraipolis.com/documento/dc_4ffce6325f57

How to cite

Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM — arXiv:2609.36111 — arXiv (en), https://arxiv.org/abs/2609.36111 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_4ffce6325f57 (Metraipolis archive dc_4ffce6325f57, sha256 54cf85ce3e4ff5117b1596431d88f82f26e278bf40a9f2c26e35f9eba28157a3)

@misc{dc4ffce6325f57,
  title = {Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM — arXiv:2609.36111},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2609.36111},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_4ffce6325f57; sha256 54cf85ce3e4ff5117b1596431d88f82f26e278bf40a9f2c26e35f9eba28157a3},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2609.36111. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

External memory interfaces (such as LPDDR5/4 and DDR5) are essential components of modern mobile, cloud, and enterprise computing systems. While memory manufacturers focus on physical DRAM die development, the vast majority of semiconductor firms design custom application ASICs that require a dedicated Memory Controller to interface with these standardized external memories. Consequently, pre-silicon design verification of the Memory Controller RTL -- acting as the Device Under Test (DUT) against a third-party DRAM Verification IP (VIP) -- is a ubiquitous and critical challenge across the global semiconductor industry. This article presents an automated, pre-silicon configuration and closed-loop initialization framework for Memory Controller verification. The proposed solution parses JEDEC timing and configuration parameters directly from the DRAM VIP's database files (such as Denali SOMA files) to configure the Memory Controller DUT's registers, while a custom Mode Register Register Abstraction Layer (MR-RAL) tracks volatile DRAM VIP states in real-time. Furthermore, a dynamic, re-compilation-free PHY initialization flow randomizes interface parameters directly in the testbench, executes on-the-fly configuration generation via system calls, and parses the resulting register write sequences at runtime. By integrating these automated methodologies into pre-silicon verification flows, engineers can eliminate setup overhead, prevent false protocol violations, and enable comprehensive randomized testing of complex PHY and Memory Controller configurations.

Tema degli esploratori: calcolo e infrastrutture (retro-catalogo arXiv: annunci del 2026-09-30 in cs.AR).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2609.36111 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-07T16:31:49.767Z dalla pagina https://arxiv.org/catchup/cs.AR/2026-09-30?abs=True (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).