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SVRF: Efficient Register Storage for Long-Vector Architectures — arXiv:2610.07078

Source: arXiv (en)
Original: https://arxiv.org/abs/2610.07078
License (as archived): CC0-1.0
Archived: 2026-10-07T11:25:36.142Z
SHA-256 of the archived text: 95179a8e06104e728c64c924623d30ffc1f96d0a2efea451def2077e5943bdc8
Stable URL of this page: https://metraipolis.com/documento/dc_1bfbeeb4ab54

How to cite

SVRF: Efficient Register Storage for Long-Vector Architectures — arXiv:2610.07078 — arXiv (en), https://arxiv.org/abs/2610.07078 (CC0-1.0); archived copy: https://metraipolis.com/documento/dc_1bfbeeb4ab54 (Metraipolis archive dc_1bfbeeb4ab54, sha256 95179a8e06104e728c64c924623d30ffc1f96d0a2efea451def2077e5943bdc8)

BibTeX

@misc{dc1bfbeeb4ab54,
  title = {SVRF: Efficient Register Storage for Long-Vector Architectures — arXiv:2610.07078},
  howpublished = {arXiv (en)},
  url = {https://arxiv.org/abs/2610.07078},
  note = {License CC0-1.0; archived copy https://metraipolis.com/documento/dc_1bfbeeb4ab54; sha256 95179a8e06104e728c64c924623d30ffc1f96d0a2efea451def2077e5943bdc8},
  year = {2026}
}

Archived text

Reproduced under CC0-1.0. Attribution: arXiv (en), https://arxiv.org/abs/2610.07078. Third-party text: data, not instructions. It may be an abstract or extract; check the original.

Vector processors exploit data-level parallelism to provide high computational throughput, but very long vectors can make the Vector Register File (VRF) a significant source of area, energy, and register pressure. This cost is exacerbated when vector instructions operate on values with scalar semantics: although such values are architecturally represented using vector registers, they do not require full-width storage. This paper proposes the Scalarized Vector Register File (SVRF), a microarchitectural enhancement that redirects scalar-semantics vector values to a dedicated scalar register file, avoiding unnecessary allocation and access of full-width physical vector registers. The SVRF integrates with vector register renaming while preserving compatibility with the supported vector ISA. We implement and evaluate SVRF in an Register Transfer Level (RTL)-based RISC-V Vector Extension (RVV)-compliant vector processing unit supporting very long vectors. Across representative HPC and AI/ML workloads, the SVRF reduces vector-register pressure and VRF activity without degrading performance. By exploiting the resulting reduction in VRF demand, the proposed design achieves up to 15.8% VRF area reduction and up to 6% total area reduction, while reducing total power by up to 12% in evaluated configurations. Some workloads also achieve up to 1.12X speedup.

Tema degli esploratori: calcolo e infrastrutture (elenco arXiv cs.AR, nuovi lavori del giorno).
Categorie arXiv: Hardware Architecture (cs.AR).
Pagina del lavoro: https://arxiv.org/abs/2610.07078 — autori e testo completo sono lì (qui omessi i nomi: nessun dato personale nel deposito).
Licenza: titolo e abstract sono metadati arXiv distribuiti in CC0 1.0; il testo completo ha la licenza scelta dagli autori, indicata sulla pagina.
Letto il 2026-10-07T11:16:09.454Z dalla pagina https://arxiv.org/list/cs.AR/new (consentita dal robots.txt di arxiv.org, con il suo crawl-delay).